1. Field of the Invention
The present invention relates to a method of manufacturing a super self-alignment technology bipolar transistor and, more particularly, a manufacturing method capable of defining a size of a base region of a super self-alignment technology bipolar transistor.
2. Description of the Related Art
A method of manufacturing a super self-alignment technology bipolar transistor is disclosed in the specification and drawings of Published Unexamined Japanese Patent Application No. 60-81862.
According to the disclosed prior art, there is provided a micropatterned bipolar transistor having a width of about 0.5 .mu.m of an emitter, a width of about 0.3 .mu.m of an insulating film for insulating the emitter from a base contact and a width of about 0.3 .mu.m of the base contact by a lithographic technique having a minimum size of 2 .mu.m. A bipolar transistor of this type is referred to as a super self-alignment technology bipolar transistor. In this specification, the super self-alignment technology bipolar transistor is referred to as an SST bipolar transistor hereinafter.
In a method of manufacturing an SST bipolar transistor disclosed in the specification and drawings of Published Unexamined Japanese Patent Application No. 60-81862, formation of a base region has the following characteristics.
A first SiO.sub.2 film is formed on a prospective bipolar transistor forming region of a major surface of an Si substrate. An Si.sub.3 N.sub.4 film having a thickness of about 1,500 1/8 is formed on the first SiO.sub.2 layer. A first poly-Si film prospectively serving as a base electrode is formed on the Si.sub.3 N.sub.4 film. An opening is formed in the first poly-Si film using lithographic techniques to expose the Si.sub.3 N.sub.4 film. An emitter electrode is prospectively formed in this opening. The surface of the first poly-Si film is oxidized to form a second SiO.sub.2 film. The second SiO.sub.2 film prospectively constitutes an insulating film for insulating an emitter from a base. The Si.sub.3 N.sub.4 film is etched by hot H.sub.3 PO.sub.4 using the first and second SiO.sub.2 films as etching masks. At this time, the Si.sub.3 N.sub.4 film located under the first poly-Si film is side-etched by about 0.7 .mu.m. The etched portion including the side-etched portion prospectively defines a size of a base region. A second poly-Si film is formed on the etched portion including the side-etched portion. In this case, the poly-Si film contacts the Si substrate at the side-etched portion and is integrated with the above first poly-Si film to prospectively constitute an outer base contact portion.
In the method of manufacturing an SST bipolar transistor disclosed in the specification and drawings of Published Unexamined Japanese Patent Application No. 60-81862, a size of a base region on a major surface of the Si substrate is defined by a size of a portion where an Si.sub.3 N.sub.4 film is etched and side-etched using an SiO.sub.2 film as an etching mask from an opening formed using lithographic techniques.
In order to increase etching selectivity of the Si.sub.3 N.sub.4 film to the SiO.sub.2 film, wet-etching must be performed using hot H.sub.3 PO.sub.4 as an etching solution. This hot H.sub.3 PO.sub.4 is a viscous liquid, and its coefficient of viscosity is high. For this reason, bubbles are easily formed in a space formed between the Si substrate and the first poly-Si film when the first Si.sub.3 N.sub.4 film having a thickness of about 1,000 to 1,500 .ANG. is side-etched. When these bubbles are formed, the hot H.sub.3 PO.sub.4 can no longer enter a region to be etched, thereby forming etching nonuniformity. For this reason, a size of a base region prospectively fomed is not uniformed. Therefore, the Si.sub.3 N.sub.4 film serving as an insulator remains at the region where the outer base contact portion will be prospectively formed to increase the resistance of the region, and in an extreme case, the region is completely insulated by the Si.sub.3 N.sub.4 film not to form the SST bipolar transistor. According to the above method of manufacturing an SST bipolar transistor, an element production probability can be estimated to be a maximum of 99.99%. With this production probability, for example, about 10 failed elements are present in a semiconductor device on which 100,000 SST bipolar transistors are integrated. That is, according to the above manufacturing method, the production probability of SST bipolar transistors, i.e., yield of elements is small, and a semiconductor device on which a large number of SST bipolar transistors are integrated cannot be provided. Even if the semiconductor device can be provided, it is very expensive.
In addition, in order to solve the problem of generating bubbles, it can be considered to perform dry etching of Si.sub.3 N.sub.4 in place of wet etching. However, etching selectivity of the Si.sub.3 N.sub.4 film to the SiO.sub.2 film is small by using dry etching techniques at present. Therefore, since the SiO.sub.2 film cannot be used as an etching mask for the Si.sub.3 N.sub.4, the Si substrate is overetched and a hole may be formed in the Si substrate. For this reason, the Si.sub.3 N.sub.4 film cannot be dry-etched in practice.
During manufacturing steps, an amount of etching is varied by variations in manufacturing atmosphere or variations in etching. Therefore, in the SST bipolar transistor manufactured in the above manufacturing method, a base region is not uniformed, thereby varying characteristics of elements.